/******************************************************************************
*
* Copyright (C) 2018 - 2028 FMSH, Inc.  All rights reserved.
*
******************************************************************************/
/******************************************************************************
*
* @file  fmsh_dmac_hw.h
*
* This file contains
*
* @note		None.
*
* MODIFICATION HISTORY:
*
*<pre>
* Ver   Who  Date     Changes
* ----- ---- -------- ---------------------------------------------
* 0.01   yl  12/20/2018  First Release
*</pre>
******************************************************************************/
#ifndef _FMSH_DMAC_HW_H_
#define _FMSH_DMAC_HW_H_

/***************************** Include Files *********************************/

/************************** Constant Definitions *****************************/

/* define DMAC register's offset*/
/* channel registers, x = 0~7*/
#define DMAC_CHX_SAR_L_OFFSET(x)		(0x0000 + 0x0058 * x)
#define DMAC_CHX_SAR_H_OFFSET(x)		(0x0004 + 0x0058 * x)
#define DMAC_CHX_DAR_L_OFFSET(x)		(0x0008 + 0x0058 * x)
#define DMAC_CHX_DAR_H_OFFSET(x)		(0x000C + 0x0058 * x)
#define DMAC_CHX_LLP_L_OFFSET(x)		(0x0010 + 0x0058 * x)
#define DMAC_CHX_LLP_H_OFFSET(x)		(0x0014 + 0x0058 * x)
#define DMAC_CHX_CTL_L_OFFSET(x)		(0x0018 + 0x0058 * x)
#define DMAC_CHX_CTL_H_OFFSET(x)		(0x001C + 0x0058 * x)
#define DMAC_CHX_SSTAT_L_OFFSET(x)		(0x0020 + 0x0058 * x)
#define DMAC_CHX_SSTAT_H_OFFSET(x)		(0x0024 + 0x0058 * x)
#define DMAC_CHX_DSTAT_L_OFFSET(x)		(0x0028 + 0x0058 * x)
#define DMAC_CHX_DSTAT_H_OFFSET(x)		(0x002C + 0x0058 * x)
#define DMAC_CHX_SSTATAR_L_OFFSET(x)	(0x0030 + 0x0058 * x)
#define DMAC_CHX_SSTATAR_H_OFFSET(x)	(0x0034 + 0x0058 * x)
#define DMAC_CHX_DSTATAR_L_OFFSET(x)	(0x0038 + 0x0058 * x)
#define DMAC_CHX_DSTATAR_H_OFFSET(x)	(0x003C + 0x0058 * x)
#define DMAC_CHX_CFG_L_OFFSET(x)		(0x0040 + 0x0058 * x)
#define DMAC_CHX_CFG_H_OFFSET(x)		(0x0044 + 0x0058 * x)
#define DMAC_CHX_SGR_L_OFFSET(x)		(0x0048 + 0x0058 * x)
#define DMAC_CHX_SGR_H_OFFSET(x)		(0x004C + 0x0058 * x)
#define DMAC_CHX_DSR_L_OFFSET(x)		(0x0050 + 0x0058 * x)
#define DMAC_CHX_DSR_H_OFFSET(x)		(0x0054 + 0x0058 * x)
/* interrupt registers*/
#define DMAC_INT_RAW_TFR_L_OFFSET			(0x02C0)
#define DMAC_INT_RAW_TFR_H_OFFSET			(0x02C4)
#define DMAC_INT_RAW_BLOCK_L_OFFSET			(0x02C8)
#define DMAC_INT_RAW_BLOCK_H_OFFSET			(0x02CC)
#define DMAC_INT_RAW_SRCTRAN_L_OFFSET		(0x02D0)
#define DMAC_INT_RAW_SRCTRAN_H_OFFSET		(0x02D4)
#define DMAC_INT_RAW_DSTTRAN_L_OFFSET		(0x02D8)
#define DMAC_INT_RAW_DSTTRAN_H_OFFSET		(0x02DC)
#define DMAC_INT_RAW_ERR_L_OFFSET			(0x02E0)
#define DMAC_INT_RAW_ERR_H_OFFSET			(0x02E4)
#define DMAC_INT_STATUS_TFR_L_OFFSET		(0x02E8)
#define DMAC_INT_STATUS_TFR_H_OFFSET		(0x02EC)
#define DMAC_INT_STATUS_BLOCK_L_OFFSET		(0x02F0)
#define DMAC_INT_STATUS_BLOCK_H_OFFSET		(0x02F4)
#define DMAC_INT_STATUS_SRCTRAN_L_OFFSET	(0x02F8)
#define DMAC_INT_STATUS_SRCTRAN_H_OFFSET	(0x02FC)
#define DMAC_INT_STATUS_DSTTRAN_L_OFFSET	(0x0300)
#define DMAC_INT_STATUS_DSTTRAN_H_OFFSET	(0x0304)
#define DMAC_INT_STATUS_ERR_L_OFFSET		(0x0308)
#define DMAC_INT_STATUS_ERR_H_OFFSET		(0x030C)
#define DMAC_INT_MASK_TFR_L_OFFSET			(0x0310)
#define DMAC_INT_MASK_TFR_H_OFFSET			(0x0314)
#define DMAC_INT_MASK_BLOCK_L_OFFSET		(0x0318)
#define DMAC_INT_MASK_BLOCK_H_OFFSET		(0x031C)
#define DMAC_INT_MASK_SRCTRAN_L_OFFSET		(0x0320)
#define DMAC_INT_MASK_SRCTRAN_H_OFFSET		(0x0324)
#define DMAC_INT_MASK_DSTTRAN_L_OFFSET		(0x0328)
#define DMAC_INT_MASK_DSTTRAN_H_OFFSET		(0x032C)
#define DMAC_INT_MASK_ERR_L_OFFSET			(0x0330)
#define DMAC_INT_MASK_ERR_H_OFFSET			(0x0334)
#define DMAC_INT_CLEAR_TFR_L_OFFSET			(0x0338)
#define DMAC_INT_CLEAR_TFR_H_OFFSET			(0x033C)
#define DMAC_INT_CLEAR_BLOCK_L_OFFSET		(0x0340)
#define DMAC_INT_CLEAR_BLOCK_H_OFFSET		(0x0344)
#define DMAC_INT_CLEAR_SRCTRAN_L_OFFSET		(0x0348)
#define DMAC_INT_CLEAR_SRCTRAN_H_OFFSET		(0x034C)
#define DMAC_INT_CLEAR_DSTTRAN_L_OFFSET		(0x0350)
#define DMAC_INT_CLEAR_DSTTRAN_H_OFFSET		(0x0354)
#define DMAC_INT_CLEAR_ERR_L_OFFSET			(0x0358)
#define DMAC_INT_CLEAR_ERR_H_OFFSET			(0x035C)
#define DMAC_INT_STATUS_INT_L_OFFSET		(0x0360)
#define DMAC_INT_STATUS_INT_H_OFFSET		(0x0364)
/* software handshaking registers*/
#define DMAC_SWHS_REQ_SRC_REG_L_OFFSET		(0x0368)
#define DMAC_SWHS_REQ_SRC_REG_H_OFFSET		(0x036C)
#define DMAC_SWHS_REQ_DST_REG_L_OFFSET		(0x0370)
#define DMAC_SWHS_REQ_DST_REG_H_OFFSET		(0x0374)
#define DMAC_SWHS_SGL_REQ_SRC_REG_L_OFFSET	(0x0378)
#define DMAC_SWHS_SGL_REQ_SRC_REG_H_OFFSET	(0x037C)
#define DMAC_SWHS_SGL_REQ_DST_REG_L_OFFSET	(0x0380)
#define DMAC_SWHS_SGL_REQ_DST_REG_H_OFFSET	(0x0384)
#define DMAC_SWHS_LST_SRC_REG_L_OFFSET		(0x0388)
#define DMAC_SWHS_LST_SRC_REG_H_OFFSET		(0x038C)
#define DMAC_SWHS_LST_DST_REG_L_OFFSET		(0x0390)
#define DMAC_SWHS_LST_DST_REG_H_OFFSET		(0x0394)
/* configuration and channel enable registers*/
#define DMAC_DMA_CFG_REG_L_OFFSET			(0x0398)
#define DMAC_DMA_CFG_REG_H_OFFSET			(0x039C)
#define DMAC_CH_EN_REG_L_OFFSET				(0x03A0)
#define DMAC_CH_EN_REG_H_OFFSET				(0x03A4)
/* miscellaneous registers*/
#define DMAC_DMA_ID_REG_L_OFFSET			(0x03A8)
#define DMAC_DMA_ID_REG_H_OFFSET			(0x03AC)
#define DMAC_DMA_TEST_REG_L_OFFSET			(0x03B0)
#define DMAC_DMA_TEST_REG_H_OFFSET			(0x03B4)
#define DMAC_DMA_COMP_PARAMS_6_L_OFFSET		(0x03C8)
#define DMAC_DMA_COMP_PARAMS_6_H_OFFSET		(0x03CC)
#define DMAC_DMA_COMP_PARAMS_5_L_OFFSET		(0x03D0)
#define DMAC_DMA_COMP_PARAMS_5_H_OFFSET		(0x03D4)
#define DMAC_DMA_COMP_PARAMS_4_L_OFFSET		(0x03D8)
#define DMAC_DMA_COMP_PARAMS_4_H_OFFSET		(0x03DC)
#define DMAC_DMA_COMP_PARAMS_3_L_OFFSET		(0x03E0)
#define DMAC_DMA_COMP_PARAMS_3_H_OFFSET		(0x03E4)
#define DMAC_DMA_COMP_PARAMS_2_L_OFFSET		(0x03E8)
#define DMAC_DMA_COMP_PARAMS_2_H_OFFSET		(0x03EC)
#define DMAC_DMA_COMP_PARAMS_1_L_OFFSET		(0x03F0)
#define DMAC_DMA_COMP_PARAMS_1_H_OFFSET		(0x03F4)
#define DMAC_DMA_COMP_ID_REG_L_OFFSET		(0x03F8)
#define DMAC_DMA_COMP_ID_REG_H_OFFSET		(0x03FC)
/***/

/* DmaCfgReg registers*/
#define DMAC_DMACFGREG_L_DMA_EN			(0x1 << 0)
/* ChEnReg registers*/
#define DMAC_CHENREG_L_CH_EN(ch)		(0x1 << (ch))
#define DMAC_CHENREG_L_CH_EN_ALL		(0xFF << 0)

#define DMAC_CHENREG_L_CH_EN_WE(ch)		(0x1 << ((ch) + 8))
#define DMAC_CHENREG_L_CH_EN_WE_ALL		(0xFF << 8)
/* Channel registers*/
#define DMAC_SAR_L_SAR              	(0xFFFFFFFF)
#define DMAC_DAR_L_DAR              	(0xFFFFFFFF)

#define DMAC_LLP_L_LMS              	(0x3 << 0)
#define DMAC_LLP_L_LOC              	((unsigned int)0x3FFFFFFF << 2)

#define DMAC_CTL_L_INT_EN           	(0x1 << 0)
#define DMAC_CTL_L_DST_TR_WIDTH     	(0x7 << 1)
#define DMAC_CTL_L_SRC_TR_WIDTH     	(0x7 << 4)
#define DMAC_CTL_L_DINC             	(0x3 << 7)
#define DMAC_CTL_L_SINC             	(0x3 << 9)
#define DMAC_CTL_L_DEST_MSIZE       	(0x7 << 11)
#define DMAC_CTL_L_SRC_MSIZE        	(0x7 << 14)
#define DMAC_CTL_L_SRC_GATHER_EN    	(0x1 << 17)
#define DMAC_CTL_L_DST_SCATTER_EN   	(0x1 << 18)
#define DMAC_CTL_L_TT_FC            	(0x7 << 20)
#define DMAC_CTL_L_DMS              	(0x3 << 23)
#define DMAC_CTL_L_SMS              	(0x3 << 25)
#define DMAC_CTL_L_LLP_DST_EN       	(0x1 << 27)
#define DMAC_CTL_L_LLP_SRC_EN       	(0x1 << 28)

#define DMAC_CTL_H_BLOCK_TS         	(0xFFF << 0)
#define DMAC_CTL_H_DONE             	(0x1 << 12)

#define DMAC_SSTAT_L_SSTAT          (0xFFFFFFFF)

#define DMAC_DSTAT_L_DSTAT          (0xFFFFFFFF)

#define DMAC_SSTATAR_L_SSTATAR      (0xFFFFFFFF)

#define DMAC_DSTATAR_L_DSTATAR      (0xFFFFFFFF)

#define DMAC_CFG_L_CH_PRIOR         (0x7 << 5)
#define DMAC_CFG_L_CH_SUSP          (0x1 << 8)
#define DMAC_CFG_L_FIFO_EMPTY       (0x1 << 9)
#define DMAC_CFG_L_HS_SEL_DST       (0x1 << 10)
#define DMAC_CFG_L_HS_SEL_SRC       (0x1 << 11)
#define DMAC_CFG_L_LOCK_CH_L        (0x3 << 12)
#define DMAC_CFG_L_LOCK_B_L         (0x3 << 14)
#define DMAC_CFG_L_LOCK_CH          (0x1 << 16)
#define DMAC_CFG_L_LOCK_B           (0x1 << 17)
#define DMAC_CFG_L_DST_HS_POL       (0x1 << 18)
#define DMAC_CFG_L_SRC_HS_POL       (0x1 << 19)
#define DMAC_CFG_L_MAX_ABRST        (0x3FF << 20)
#define DMAC_CFG_L_RELOAD_SRC       (0x1 << 30)
#define DMAC_CFG_L_RELOAD_DST       ((unsigned int)0x1 << 31)

#define DMAC_CFG_H_FCMODE           (0x1 << 0)
#define DMAC_CFG_H_FIFO_MODE        (0x1 << 1)
#define DMAC_CFG_H_PROTCTL          (0x7 << 2)
#define DMAC_CFG_H_DS_UPD_EN        (0x1 << 5)
#define DMAC_CFG_H_SS_UPD_EN        (0x1 << 6)
#define DMAC_CFG_H_SRC_PER          (0xF << 7)
#define DMAC_CFG_H_DEST_PER         (0xF << 11)

#define DMAC_SGR_L_SGI              (0xFFFFF << 0)
#define DMAC_SGR_L_SGC              ((unsigned int)0xFFF << 20)

#define DMAC_DSR_L_DSI              (0xFFFFF << 0)
#define DMAC_DSR_L_DSC              ((unsigned int)0xFFF << 20)
/* Interrupt registers*/
#define DMAC_INT_RAW_STAT_CLR(ch)   (0x1 << (ch))
#define DMAC_INT_RAW_STAT_CLR_ALL   (0xFF << 0)

#define DMAC_INT_MASK_L(ch)         (0x1 << (ch))
#define DMAC_INT_MASK_L_ALL         (0xFF << 0)
#define DMAC_INT_MASK_L_WE(ch)      (0x1 << ((ch) + 8))
#define DMAC_INT_MASK_L_WE_ALL      (0xFF << 8)

#define DMAC_STATUSINT_L_TFR        (0x1 << 0)
#define DMAC_STATUSINT_L_BLOCK      (0x1 << 1)
#define DMAC_STATUSINT_L_SRCTRAN    (0x1 << 2)
#define DMAC_STATUSINT_L_DSTTRAN    (0x1 << 3)
#define DMAC_STATUSINT_L_ERR        (0x1 << 4)
/* SoftWare HandShaking registers*/
#define DMAC_SW_HANDSHAKE_L(ch)     (0x1 << (ch))
#define DMAC_SW_HANDSHAKE_L_WE(ch)  (0x1 << ((ch) + 8))
/* DmaldReg registers*/
#define DMAC_DMALD_L_DMA_ID         (0xFFFFFFFF)
/* DmaTestReg registers*/
#define DMAC_DMATESTREG_L_TEST_SLV_IF (0x1 << 0)
/* DMA_COMP_PARAMS registers*/
#define DMAC_DMACOMPVER_L_DMACOMPVER  (0xFFFFFFFF)

#define DMAC_PARAM_CHX_DTW           (0x7 << 0)
#define DMAC_PARAM_CHX_STW           (0x7 << 3)
#define DMAC_PARAM_CHX_STAT_DST      (0x1 << 6)
#define DMAC_PARAM_CHX_STAT_SRC      (0x1 << 7)
#define DMAC_PARAM_CHX_DST_SCA_EN    (0x1 << 8)
#define DMAC_PARAM_CHX_SRC_GAT_EN    (0x1 << 9)
#define DMAC_PARAM_CHX_LOCK_EN       (0x1 << 10)
#define DMAC_PARAM_CHX_MULTI_BLK_EN  (0x1 << 11)
#define DMAC_PARAM_CHX_CTL_WB_EN     (0x1 << 12)
#define DMAC_PARAM_CHX_HC_LLP        (0x1 << 13)
#define DMAC_PARAM_CHX_FC            (0x3 << 14)
#define DMAC_PARAM_CHX_MAX_MULT_SIZE (0x7 << 16)
#define DMAC_PARAM_CHX_DMS           (0x7 << 19)
#define DMAC_PARAM_CHX_LMS           (0x7 << 22)
#define DMAC_PARAM_CHX_SMS           (0x7 << 25)
#define DMAC_PARAM_CHX_FIFO_DEPTH    (0x7 << 28)

#define DMAC_PARAM_CH0_MULTI_BLK_TYPE  (0xF << 0)
#define DMAC_PARAM_CH1_MULTI_BLK_TYPE  (0xF << 4)
#define DMAC_PARAM_CH2_MULTI_BLK_TYPE  (0xF << 8)
#define DMAC_PARAM_CH3_MULTI_BLK_TYPE  (0xF << 12)
#define DMAC_PARAM_CH4_MULTI_BLK_TYPE  (0xF << 16)
#define DMAC_PARAM_CH5_MULTI_BLK_TYPE  (0xF << 20)
#define DMAC_PARAM_CH6_MULTI_BLK_TYPE  (0xF << 24)
#define DMAC_PARAM_CH7_MULTI_BLK_TYPE  ((unsigned int)0xF << 28)

#define DMAC_PARAM_BIG_ENDIAN        (0x1 << 0)
#define DMAC_PARAM_INTR_IO           (0x3 << 1)
#define DMAC_PARAM_MABRST            (0x1 << 3)
#define DMAC_PARAM_NUM_CHANNELS      (0x7 << 8)
#define DMAC_PARAM_NUM_MASTER_INT    (0x3 << 11)
#define DMAC_PARAM_S_HDATA_WIDTH     (0x3 << 13)
#define DMAC_PARAM_M1_HDATA_WIDTH    (0x3 << 15)
#define DMAC_PARAM_M2_HDATA_WIDTH    (0x3 << 17)
#define DMAC_PARAM_M3_HDATA_WIDTH    (0x3 << 19)
#define DMAC_PARAM_M4_HDATA_WIDTH    (0x3 << 21)
#define DMAC_PARAM_NUM_HS_INT        (0x1F << 23)
#define DMAC_PARAM_ADD_ENCODED_PARAMS (0x1 << 28)
#define DMAC_PARAM_STATIC_ENDIAN_SELECT (0x1 << 29)

#define DMAC_PARAM_CH0_MAX_BLK_SIZE  (0xF << 0)
#define DMAC_PARAM_CH1_MAX_BLK_SIZE  (0xF << 4)
#define DMAC_PARAM_CH2_MAX_BLK_SIZE  (0xF << 8)
#define DMAC_PARAM_CH3_MAX_BLK_SIZE  (0xF << 12)
#define DMAC_PARAM_CH4_MAX_BLK_SIZE  (0xF << 16)
#define DMAC_PARAM_CH5_MAX_BLK_SIZE  (0xF << 20)
#define DMAC_PARAM_CH6_MAX_BLK_SIZE  (0xF << 24)
#define DMAC_PARAM_CH7_MAX_BLK_SIZE  ((unsigned int)0xF << 28)

/* DMA Component ID registers*/
#define DMAC_IDREG_L_DMA_COMP_TYPE     (0xFFFFFFFF)
#define DMAC_IDREG_H_DMA_COMP_VERSION     (0xFFFFFFFF)
/*****/

/**************************** Type Definitions *******************************/

/***************** Macros (Inline Functions) Definitions *********************/

/************************** Function Prototypes ******************************/


#endif /* #ifndef _FMSH_DMAC_HW_H_ */
